The present disclosure relates to improving the yield rate of a multiprocessor semiconductor chip. More particularly, the disclosure relates to a system and a method for providing at least one redundant processor core in the multiprocessor semiconductor chip.
In order to increase functionality and performance, microprocessor chips are increasingly being built with multiple processor cores. This has become feasible as, with shrinking device technologies, a size of a typical processor core is shrinking, so that it becomes possible to add extra processor cores onto a semiconductor chip. On the other hand, notwithstanding the shrinking device technologies (e.g., 22 nm CMOS technology), multiprocessor semiconductor chips typically have large chip sizes (e.g., 6 cm2), as demands on the number of processors also leads to a commensurate increase in cache size and other on-chip resources. However, manufacturing yield for semiconductor chips generally decreases steeply with increasing semiconductor chip size, if the yield is limited by random defects. Decreasing yield with increasing semiconductor chip size leads to markedly increasing cost with the increasing semiconductor chip size.
This phenomenon has been observed before with memory chips (or memory arrays on logic chips): as technologies shrank and memory sizes grew, defect-limited yield became a problem. The well-known solution to decreasing yield rate of memory device has been to introduce redundancy into the memory arrays, i.e. redundant word lines or redundant bit lines. At a manufacturing test, fails in an array are diagnosed, and it is determined whether the array is repairable by mapping out certain word and/or bit lines associated with the fails, effectively replacing them with the provided redundant word and/or bit lines. Configuration information (e.g., mapping logical addresses of failed word/bit lines to physical addresses of redundant word/bit lines) for these array repairs are typically encoded into fuses (i.e., non-volatile storage) on the chip. As a result of this redundancy scheme, there is no noticeable difference to the end user between a semiconductor chip with perfect arrays and a chip with repaired arrays.
The impact of array redundancy on yield rate is remarkable: as long as enough redundancy is provided so that all arrays are fixable, the number and size of redundant arrays on a semiconductor chip will have very little effect on the yield rate. The positive effect on the yield rate and chip cost due to redundancy far outweighs the negative effect due to the larger array sizes with the additional redundant word and/or bit lines.